View CY62138EV30_1202797.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CY62138EV30 mobl ? 2 mbit (256k x 8) mobl ? static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-05577 rev. *c revised january 17, 2011 features very high speed: 45 ns ? wide voltage range: 2.20 v to 3.60 v pin compatible with cy62138cv30 ultra low standby power ? typical standby current: 1 ? a ? maximum standby current: 7 ? a ultra low active power ? typical active current: 2 ma at f = 1 mhz easy memory expansion with ce and oe features automatic power down when deselected complementary metal oxide semiconducor (cmos) for optimum speed and power offered in pb-free 36-ball ball grid array (bga) package functional description the CY62138EV30 [1] is a high performance cmos static ram organized as 256k words by eight bits. this device features advanced circuit design to provide ultra low active current. this is ideal for providing more battery life? (mobl ? ) in portable applications such as cellular telephones. the device also has an automatic power down feature that significantly reduces power consumption. the device can be put into standby mode reducing power consumption when deselected (ce high). writing to the device is accomplished by taking chip enable (ce ) and write enable (we ) inputs low. data on the eight i/o pins (i/o 0 through i/o 7 ) is then written into the location specified on the address pins (a 0 through a 18 ). reading from the device is accomplished by taking chip enable (ce ) and output enable (oe ) low while forcing write enable (we ) high. under these conditions, the contents of the memory location specified by the address pins appear on the i/o pins. the eight input and output pins (i/o 0 through i/o 7 ) are placed in a high impedance state when the device is deselected (ce high), the outputs are disabled (oe high), or during a write operation (ce low and we low). note 1. for best practice recommendations, refer to the cypre ss application note ?sram system design guidelines? on http://www.cypress.com . logic block diagram a 1 column decoder row decoder sense amps data in drivers power down we oe i/o 0 i/o 1 i/o 2 i/o 3 256k x 8 array i/o 7 i/o 6 i/o 5 i/o 4 a 0 a 12 ce a 13 a 14 a 15 a 16 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 a 11 a 17 [+] feedback
CY62138EV30 mobl ? document #: 38-05577 rev. *c page 2 of 12 contents pin configuration .............................................................. 3 product portfolio .............................................................. 3 maximum ratings ............................................................. 4 electrical characteristics 4.................................................. capacitance ...................................................................... 5 thermal resistance .......................................................... 5 data retention characteristics ....................................... 5 data retention waveform ................................................ 5 switching characteristics ................................................ 6 switching waveforms ...................................................... 6 ordering information ........................................................ 9 ordering code definition ....... ...................................... 9 package diagram ............................................................ 10 acronyms ........................................................................ 10 document conventions ................................................. 10 units of measure ....................................................... 10 document history page ................................................. 11 sales, solutions, and legal information ...................... 12 worldwide sales and design s upport ......... .............. 12 products .................................................................... 12 psoc solutions ......................................................... 12 [+] feedback
CY62138EV30 mobl ? document #: 38-05577 rev. *c page 3 of 12 pin configuration [2] product portfolio product v cc range (v) speed (ns) power dissipation operating i cc (ma) standby i sb2 ( ? a) f = 1 mhz f = f max min typ [3] max typ [3] max typ [3] max typ [3] max CY62138EV30ll 2.2 3.0 3.6 45 2 2.5 15 20 1 7 a 15 v cc a 13 a 12 a 5 nc we a 7 i/o 4 i/o 5 a 4 i/o 6 i/o 7 v ss a 11 a 10 a 1 v ss i/o 0 a 2 a 8 a 6 a 3 a 0 v cc i/o 1 i/o 2 i/o 3 a 17 nc a 16 ce oe a 9 a 14 d e b a c f g h nc top view fbga notes 2. nc pins are not connected on the die. 3. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ.) , t a = 25 c. [+] feedback
CY62138EV30 mobl ? document #: 38-05577 rev. *c page 4 of 12 maximum ratings exceeding the maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature................................. ?65 c to +150 c ambient temperature with power applied ............................................. 55 c to +125 c supply voltage to ground potential ....................................... ?0.3 v to v cc(max) + 0.3 v dc voltage applied to outputs in high z state [4,5] ......................... ?0.3 v to v cc(max) + 0.3 v dc input voltage [4,5] ...................... ?0.3 v to v cc(max) + 0.3 v output current into outputs (low) .............................. 20 ma static discharge voltage.......................................... > 2001 v (per mil-std-883, method 3015) latch-up current ..................................................... > 200 ma product range ambient temperature v cc [6] CY62138EV30ll industrial ?40 c to +85 c 2.2 v to 3.6 v electrical characteristics over the operating range parameter description test conditions CY62138EV30-45 unit min typ [7] max v oh output high voltage i oh = ?0.1 ma v cc = 2.20 v 2.0 ? ? v i oh = ?1.0 ma v cc = 2.70 v 2.4 ? ? v v ol output low voltage i ol = 0.1 ma v cc = 2.20 v ? ? 0.4 v i ol = 2.1 ma v cc = 2.70 v ? ? 0.4 v v ih input high voltage v cc = 2.2 v to 2.7 v 1.8 ? v cc + 0.3v v v cc = 2.7 v to 3.6 v 2.2 ? v cc + 0.3v v v il input low voltage v cc = 2.2 v to 2.7 v ?0.3 ? 0.6 v v cc = 2.7 v to 3.6 v ?0.3 ? 0.8 v i ix input leakage current gnd < v i < v cc ?1 ? +1 ? a i oz output leakage current gnd < v o < v cc , output disabled ?1 ? +1 ? a i cc v cc operating supply current f = f max = 1/t rc v cc = v ccmax i out = 0 ma cmos levels ?1520ma f = 1 mhz ? 2 2.5 ma i sb1 [8] automatic ce power down current ? cmos inputs ce > v cc ? ? 0.2 v, v in > v cc ? 0.2 v, v in < 0.2 v), f = f max (address and data only), f = 0 (oe , and we ), v cc = 3.60 v ?17 ? a i sb2 [8] automatic ce power down current ? cmos inputs ce > v cc ? 0.2 v, v in > v cc ? 0.2 v or v in < 0.2 v, f = 0, v cc = 3.60 v ?17 ? a notes 4. v il(min.) = ?2.0 v for pulse durations less than 20 ns. 5. v ih(max) = v cc +0.75 v for pulse durations less than 20 ns. 6. full device ac operation assumes a 100 ? s ramp time from 0 to v cc (min.) and 200 ? s wait time after v cc stabilization. 7. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc(typ.) , t a = 25 c 8. chip enable (ce ) must be tied to cmos levels to meet the i sb1 / i sb2 / i ccdr specification. other inputs can be left floating. [+] feedback
CY62138EV30 mobl ? document #: 38-05577 rev. *c page 5 of 12 capacitance parameter [9] description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = v cc(typ.) 10 pf c out output capacitance 10 pf thermal resistance parameter [9] description test conditions bga unit ? ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, four-layer printed circuit board 72 ? c / w ? jc thermal resistance (junction to case) 8.86 ? c / w figure 1. ac test loads and waveforms parameters 2.50 v 3.0 v unit r1 16667 1103 ? r2 15385 1554 ? r th 8000 645 ? v th 1.20 1.75 v data retention characteristics (over the operating range) parameter description conditions min typ [10] max unit v dr v cc for data retention 1 ? ? v i ccdr [11] data retention current v cc = 1v, ce > v cc ?? 0.2 v, v in > v cc ?? 0.2 v or v in < 0.2 v ?0.8 3 ? a t cdr [9] chip deselect to data retention time 0 ? ? ns t r [12] operation recovery time 45 ? ? ns v cc v cc output r2 30 pf including jig and scope gnd 90% 10% 90% 10% output v th equivalent to: thvenin equivalent all input pulses r th r1 fall time: 1 v/ns rise time: 1 v/ns data retention waveform notes 9. tested initially and after any design or process changes that may affect these parameters. 10. typical values are included for reference only and are not guar anteed or tested. typical values are measured at vcc = vcc(ty p), ta = 25 c 11. chip enable (ce ) must be tied to cmos levels to meet the i sb1 / i sb2 / i ccdr specification. other inputs can be left floating. 12. full device ac operation requires linear v cc ramp from v dr to v cc(min.) > 100 ? s or stable at v cc(min.) ? 100 ? s. 1.5 v t cdr v dr > 1.5 v data retention mode t r ce v cc v cc (min.) [+] feedback
CY62138EV30 mobl ? document #: 38-05577 rev. *c page 6 of 12 switching characteristics over the operating range parameter [13] description 45 ns unit min max read cycle t rc read cycle time 45 ? ns t aa address to data valid ? 45 ns t oha data hold from address change 10 ? ns t ace ce low to data valid ? 45 ns t doe oe low to data valid ? 22 ns t lzoe oe low to low z [14] 5?ns t hzoe oe high to high z [14,15] ?18ns t lzce ce low to low z [14] 10 ? ns t hzce ce high to high z [14,15] ?18ns t pu ce low to power-up 0 ? ns t pd ce high to power-up ? 45 ns write cycle [16] t wc write cycle time 45 ? ns t sce ce low to write end 35 ? ns t aw address setup to write end 35 ? ns t ha address hold from write end 0 ? ns t sa address setup to write start 0 ? ns t pwe we pulse width 35 ? ns t sd data setup to write end 25 ? ns t hd data hold from write end 0 ? ns t hzwe we low to high z [14,15] ?18ns t lzwe we high to low z [14] 10 ? ns switching waveforms figure 2. read cycle no. 1: address transition controlled [17, 18] notes 13. test conditions for all parameters other than three-state parame ters assume signal transition ti me of 3 ns or less (1 v/ns), timing reference levels of v cc(typ) /2, input pulse levels of 0 to v cc(typ) , and output loading of the specified i ol /i oh as shown in ac test loads and waveforms . 14. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 15. t hzoe , t hzce , and t hzwe transitions are measured when the output enter a high impedance state. 16. the internal write time of the memory is defined by the overlap of we , ce = v il . all signals must be active to initia te a write and any of these signals can terminate a write by going inactive. the data input set-up and hold timing should be referenced to the edge of the signal that terminates the write. 17. device is continuously selected. oe , ce = v il . 18. we is high for read cycle. address data out previous data valid data valid t rc t aa t oha [+] feedback
CY62138EV30 mobl ? document #: 38-05577 rev. *c page 7 of 12 figure 3. read cycle no. 2: oe controlled [19, 20] figure 4. write cycle no. 1: we controlled [21, 23] switching waveforms (continued) 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu data out high impedance impedance i cc i sb t hzoe t hzce t pd oe ce high v cc supply current address t hd t sd t pwe t sa t ha t aw t wc data i/o address ce we oe t hzoe data in valid note 22 t sce notes 19. we is high for read cycle. 20. address valid prior to or coincident with ce transition low. 21. data i/o is high impedance if oe = v ih . 22. during this period, the i/os are in output state and input signals should not be applied. 23. if ce goes high simultaneously with we high, the output remains in high impedance state. [+] feedback
CY62138EV30 mobl ? document #: 38-05577 rev. *c page 8 of 12 figure 5. write cycle no. 2 ce controlled [24, 25] figure 6. write cycle no. 3 : we controlled, oe low [25] switching waveforms (continued) t wc data in valid t aw t sa t pwe t ha t hd t sd t sce ce address we data i/o oe data i/o address t hd t sd t lzwe t sa t ha t aw t wc ce t hzwe data in valid note 26 t pwe t sce we truth table ce we oe inputs/outputs mode power h [27] x x high z deselect/power-down standby (i sb ) l h l data out (i/o 0 ?i/o 7 ) read active (i cc ) l h h high z output disabled active (i cc ) l l x data in (i/o 0 ?i/o 7 ) write active (i cc ) notes 24. data i/o is high impedance if oe = v ih 25. if ce goes high simultaneously with we high, the output remains in high impedance state. 26. during this period, the i/os are in output state and input signals should not be applied. 27. chip enable (ce ) must be tied to cmos levels to meet the i sb1 / i sb2 / i ccdr specification. other inputs can be left floating. [+] feedback
CY62138EV30 mobl ? document #: 38-05577 rev. *c page 9 of 12 ordering information speed (ns) ordering code package diagram package type operating range 45 CY62138EV30ll-45bvxi 51-85149 36-ball very fine pi tch bga (6 mm 8 mm 1 mm) (pb-free) industrial ordering code definition cy 621 3 8e v30 ll 45 xxx x company id: cy = cypress mobl sram family density = 2 mbit bus width = x8 e = 90nm technology voltage range = 3 v typical low power speed grade package type bvx: vfbga (pb-free) temperature grades i = industrial [+] feedback
CY62138EV30 mobl ? document #: 38-05577 rev. *c page 10 of 12 acronyms document conventions units of measure package diagram figure 7. 36-ball vfbga (6 x 8 x 1 mm) (51-85149) 51-85149-*d acronym description cmos complementary metal oxide semiconductor i/o input/output sram static random access memory vfbga very fine ball gird array tsop thin small outline package symbol unit of measure c degrees celsius ? a microamperes ma milliampere mhz megahertz ns nanoseconds pf picofarads v volts ? ohms w watts [+] feedback
CY62138EV30 mobl ? document #: 38-05577 rev. *c page 11 of 12 document history page document title: CY62138EV30 mobl ? 2 mbit (256k x 8) mobl ? static ram document number: 38-05577 rev. ecn no. orig. of change submission date description of change ** 237432 aju see ecn new data sheet *a 427817 nxr see ecn removed 35 ns speed bin removed ?l? version removed 32-pin tsopii package from product offering. changed ball c3 from dnu to nc. removed the redundant footnote on dnu. moved product portfolio from page # 3 to page #2. changed i cc (max) value from 2 ma to 2.5 ma and i cc (typ) value from 1.5 ma to 2 ma at f = 1 mhz changed i cc (typ) value from 12 ma to 15 ma at f = f max =1/t rc changed i sb1 and i sb2 typ. values from 0.7 ? a to 1 ? a and max. values from 2.5 ? a to 7 ? a. changed v cc stabilization time in footnote #7 from 100 ? s to 200 ? s changed the ac test load capacitance from 50pf to 30pf on page# 4 changed v dr from 1.5v to 1v on page# 4. changed i ccdr from 1 ? a to 3 ? a in the data retention characteristics table on page # 4. corrected t r in data retention characteristics from 100 ? s to t rc ns changed t oha , t lzce , t lzwe from 6 ns to 10 ns changed t hzoe , t hzce , t hzwe from 15 ns to 18 ns changed t lzoe from 3 ns to 5 ns changed t sce and t aw from 40 ns to 35 ns changed t sd from 20 ns to 25 ns changed t pwe from 25 ns to 35 ns updated the ordering information table and replaced package name column with package diagram. *b 2604685 vkn/pyrs 11/12/08 added footnote 7 related to i sb2 and i ccdr *c 3143896 rame 01/17/2011 updated datasheet as per new template added ordering code definition added acronyms and units of measure table converted all tablenotes to footnote updated package diagram 51-85149 from *c to *d [+] feedback
document #: 38-05577 rev. *c revised january 17, 2011 page 12 of 12 all products and company names mentioned in this document may be the trademarks of their respective holders. CY62138EV30 mobl ? ? cypress semiconductor corporation, 2008-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress.com/sales. products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

▲Up To Search▲

Price & Availability of CY62138EV30

	To Download CY62138EV30 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .